I turn tough constraints into reliable systems across the full stack—low-level firmware, RF experiments, FPGA DSP and the high-level software that orchestrates it all. Working shoulder-to-shoulder with teammates, I focus on clear interfaces, measurable performance and calm integrations.
Embedded systems • RF / analog computing • FPGA acceleration • Team coordination
Coordinated the rover’s electronics & embedded stack with fellow subsystem leads: STM32/ESP32 avionics, a CRC-hardened SPI layer and integration reviews. The real win was ~120 teammates across 7 subsystems plugging together without drama.
In a small research team we built a 2.4 GHz tunable metasurface and an optical GELU emulator to explore low-power activations – guided by CST sims, VNA sweeps and Python/C++ pipelines.
With astronomers at EPFL we pipelined a Zynq-based DSP chain that extracts Doppler-shifted 21 cm hydrogen lines in real time, iterating side-by-side on latency, power and spectral resolution.
CI for firmware, interface docs, checklists – the “boring” glue that keeps people moving. As IEEE EPFL comms lead I helped grow engagement 30%, and on Xplore the same habits kept subsystems aligned.
Happy to dig into specs, constraints and trade-offs.
