Eliot Abramo

I build reconfigurable hardware for real-time inference in places nobody can reach to fix it — a detector at CERN, a payload in orbit, a telescope array. The work runs from the board and the RTL up to the compiler that targets it. MSc in microelectronics at EPFL, and a research assistant on a CGRA toolchain at EPFL ESL.

Portrait of Eliot Abramo
1.25 %

Gap between hardware-measured latency and the vendor simulation flow, through an AI Engine array on a Versal ACAP. The agreement is the result: the model was right before the board existed.

CERN · CMS L1 trigger
1st of 25

European Rover Challenge 2025, 2180.4 of 3000 points. Lead engineer for the rover’s electronics.

EPFL Xplore
PDR + CDR

ESA reviews cleared for payload electronics qualified through thermal vacuum, vibration and shock.

SpaceLocker
C → CGRA

Compiler, tooling and a design-space library taking kernels onto a reconfigurable array for the SKA.

EPFL ESL / SEAMS
Now Research assistant — CGRA toolchain, DMA engine and HELIOS · EPFL ESL / SEAMS
Now MSc, Electrical & Electronic Engineering — Microelectronics · EPFL
2026 FPGA engineer, CMS Level-1 Trigger · CERN openlab, DAQ team
2026 ASTRA — CGRA toolchain for the Square Kilometre Array · EPFL ESL / SEAMS
2025–26 Payload electronics and flight software, ECSS-qualified · SpaceLocker, Toulouse
2024–25 Lead system engineer — 1st place, European Rover Challenge 2025 · EPFL Xplore

All work → Curriculum vitae → Get in touch →

01

The stack, end to end

Most hardware careers specialise into one band and stay there. Mine has not. The same hands characterised a PIN-diode metasurface on a vector network analyser and wrote compiler passes that target a reconfigurable array — and in between, the boards, the flight software and the transport stacks that connect the two.

The range is the point rather than a coincidence. Accelerators fail at the seams: the clock-domain crossing, the memory traffic nobody budgeted for, the reliability number that arrives after the design is frozen. Those seams are only visible from both sides.

Fig. 1 — Every band names work that exists and is written up. Nothing here is aspirational.
02

Selected work

Everything else →

03

In the field

An alignment target seen through a lens in a cage mount on an optical bench, green ring and red crosshair in focus.
Beam alignment on the optical bench at the Laboratory of Wave Engineering.
Presenting the rover avionics boards on stage, with PHOENYX 5.0 in front of the screen.
Presenting the avionics boards, with PHOENYX 5.0 on stage.
An optical breadboard inside a dark enclosure, with cage-system mounts, lenses and a red beam spot.
Mounts, lenses and the beam path, mid-alignment.
Four team members standing behind the EPFL Xplore PHOENYX 5.0 rover.
PHOENYX 5.0, the EPFL Xplore rover.
Custom 18650 lithium-ion battery pack part-built on a bench, balance leads out, two multimeters attached.
Building a custom 18650 pack, balance leads under test.
Team working on the rover in the pit, one member driving it from a laptop and controller.
Pit work — driving the rover from a laptop during testing.
Finished battery pack wrapped and terminated with an XT60 connector and balance harness.
The same pack, wrapped and terminated.
Team gathered at an ERC electrical and power design review, board renders on the screen behind.
ERC electrical and power review.
04

Technical notes

Short write-ups of things I measured or argued, published so they can be read rather than claimed. Each one names what it does not establish as clearly as what it does.

N01

Measured against your own flow: a VEK280 latency note

Hardware latency landed 1.25 % from aiesimulator, but only because both probes sat inside the programmable-logic domain. Includes the honest crossover where an AI Engine array stops beating a plain DSP implementation.

CERN openlab · CMS Level-1 Trigger
Versal ACAP · AI Engine · AXI4-Stream · Vitis 2026 → N02

Reconfigurable compute under orbital thermal and radiation constraints

In an orbital data centre the radiator, not the die, sets sustained throughput. Why that argues for a fabric with a real degraded mode, and where fault-recovery authority has to live.

Written September 2026
CGRA · thermal · SEU mitigation · ECSS 2026 →

All notes →

05

What I am looking for

Work FPGA and CGRA engineering — accelerator data paths, toolchains, and hardware that has to hold a latency number. Research or product, either way.
Domains Particle physics instrumentation, space and payload electronics, radio astronomy, safety-critical embedded systems.
Format A long internship, a master thesis, or a first full-time role. I am not treating those as different ambitions.
Available Placements from early 2027, and available now to talk about one.
Based Lausanne, Switzerland. Swiss and EU citizenship, so no sponsorship is needed anywhere in Switzerland or the EU. Relocation elsewhere is my problem, not yours.
Best way in A specific technical question. Email lands faster than the form.

eliot.abramo@epfl.ch → Technical notes → About → Curriculum vitae →