About Me
In short
I pride myself on being a full-stack engineer that can comfortably sit at the boundary between hardware and software. With projects ranging RTL and HW design on FPGAs and SOCs to custom automation tools for Kicad coded in python, I understand and can design a full architecture system for high constraint environments as well as the insfrastructure surrounding them.
Qualifications
MSc student in Electrical & Electronic Engineering (Microelectronics) at EPFL. Building reconfigurable hardware for real-time AI inference in extreme environments and high performance/ultra-low latency computing.
Most recently at CERN openlab where I built the FPGA programmable-logic pipeline feeding a real-time anomaly-detection model on the CMS Level-1 trigger.
EPFL's Embedded Systems Lab, building a CGRA toolchain for HPC under the SEAMS SKA project.
Also shipped flight electronics for an orbital payload at SpaceLocker, and led electronics and avionics for the rover that won the 2025 European Rover Challenge.
What I work on
- FPGA and reconfigurable compute. At CERN openlab I built the programmable-logic streaming path feeding a transformer to the AI Engine array on a Versal ACAP, and measured it in hardware at 34.02 µs — within 1.25 % of simulation. At EPFL ESL I work on a CGRA toolchain: the ASTRA work targeting Square Kilometre Array signal processing, and currently the DMA engine and HELIOS.
- Space payload electronics. At SpaceLocker I designed, built and qualified payload electronics — power conditioning, data handling, watchdog and safing — and wrote flight software in C and Rust under ECSS constraints. The hardware cleared ESA PDR and CDR and passed thermal vacuum, vibration and shock qualification.
- Rover avionics. Two years on EPFL Xplore, the last as lead system engineer for the electronics and embedded systems on the rover that won the European Rover Challenge 2025 — first of 25 on-site teams.
- RF and analog. A year at the Laboratory of Wave Engineering on physical nonlinearities as analog neuron activations — a tunable 2.4 GHz PIN-diode metasurface, and an optical GELU.
- Design tooling. Three published KiCad plugins covering multi-board projects, ECSS reliability budgets and thermal analysis for vacuum — each one written because the manual workflow was costing a design cycle.
How I work
- Design the failure paths first. Timeouts, CRCs, asserts — demos should not be adrenaline sports.
- Constraints are fuel. Power, latency, EMI — the edges are what force a design to be good rather than merely different.
- Measure, do not guess. VNAs, logic analysers, in-fabric probes. Truth lives in traces, and a simulation is a hypothesis until the board agrees with it.
- Say what a result does not show. Every case study here ends with its own limits. A number you cannot bound is not a number.
- If others cannot maintain it, it is not done. Interface specs, diagrams and clear APIs are the part that survives people leaving.
Stack
| Reconfigurable | Versal ACAP and AI Engine, Zynq / PYNQ, Vivado, Vitis HLS, AXI4-Stream, CDC design |
|---|---|
| Compilers & CGRA | MLIR, Compigra, ILP mapping and modulo scheduling, design-space exploration |
| Languages | C, C++, Rust, Python, VHDL, MATLAB, Julia, Bash |
| Embedded | STM32, ESP32, Zephyr, FreeRTOS, CAN, SPI, I²C, UART, HIL/SIL |
| Space | ECSS, IEC TR 62380, TVAC, vibration and shock testing, PDR/CDR, redundancy and safing |
| RF & analog | Metasurface design, phased-array beamforming, VNA, CST Studio, LTspice |
| Tools | KiCad, Git, STM32CubeIDE, Linux, Fusion 360 |
| Languages spoken | English and French (fluent), Spanish (conversational) |
Education
| EPFL — MSc | Electrical & Electronic Engineering, microelectronics · 2025– |
|---|---|
| EPFL — BSc | Electrical & Electronic Engineering, bilingual EN/FR · 2022–2025 |
| JESS Dubai — IB | 43 / 45 · 2018–2022 |
Awards
- European Rover Challenge 2025 — 1st place overall, first of 25 on-site teams with 2180.4 of 3000 points, plus the Drone Excellency Award.
- Young Founders Summit Asia 2019 — top 9 of over 600 teams at the Beijing finals, for a MOSFET design seven times smaller than commercial parts.
- 4x4 in Schools, UAE — top 13 nationally, Innovation Award, Yas Marina finals.